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NXP Semiconductors /QN908XC /CTIMER0 /PWMC

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Interpret as PWMC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MATCH)PWMEN0 0 (MATCH)PWMEN1 0 (MATCH)PWMEN2 0 (MATCH)PWMEN3

PWMEN2=MATCH, PWMEN1=MATCH, PWMEN3=MATCH, PWMEN0=MATCH

Description

PWM Control Register. The PWMCON enables PWM mode for the external match pins.

Fields

PWMEN0

PWM mode enable for channel0.

0 (MATCH): Match. CT32Bn_MAT0 is controlled by EM0.

1 (PWM): PWM. PWM mode is enabled for CT32Bn_MAT0.
PWMEN1

PWM mode enable for channel1.

0 (MATCH): Match. CT32Bn_MAT01 is controlled by EM1.

1 (PWM): PWM. PWM mode is enabled for CT32Bn_MAT1.
PWMEN2

PWM mode enable for channel2.

0 (MATCH): Match. CT32Bn_MAT2 is controlled by EM2.

1 (PWM): PWM. PWM mode is enabled for CT32Bn_MAT2.
PWMEN3

PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.

0 (MATCH): Match. CT32Bn_MAT3 is controlled by EM3.

1 (PWM): PWM. PWM mode is enabled for CT132Bn_MAT3.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data